1. Field of the Invention
The present disclosure relates to a semiconductor memory device and a method for operating the same. The semiconductor memory device is a field effect transistor type semiconductor memory device having a gate insulation film composed of a ferroelectric film.
2. Description of the Related Art
Japanese Laid-open patent application publication No. Hei 08-335645 (Hereinafter, Patent Literature 1) discloses a semiconductor memory device capable of memorizing multi-value data. FIG. 6(a) shows the semiconductor memory device disclosed in Patent Literature 1. In FIG. 6(a), the reference sign 101 indicates a semiconductor region. The reference signs 102 and 103 indicate a source region and a drain region. The reference sign 104 indicates a channel-forming region. The reference sign 105 indicates a ferroelectric film. The reference sign 106 indicates a gate electrode. The reference sign 107 indicates a back electrode. The reference sign 108 indicates an insulating film. When multi-value data are written into the semiconductor memory device, a predetermined voltage (in FIG. 6(b), as one example, +5 volts) is applied to the back electrode 107 to cause a channel to be an inversion state, thereby setting the voltages of the source region 102 and the drain region 103 the same as the voltage of the channel. Subsequently, a voltage applied to the gate electrode 106 is adjusted according to the multi-value data. Namely, the current flowing through the channel is varied depending on the voltage applied to the gate electrode 106, which is in contact with the ferroelectric film 105.
The semiconductor memory device disclosed in Patent Literature 1 memorizes multi-value data by varying only the voltage applied to the gate electrode 106 contacting the ferroelectric film 105. However, the resistance value of the channel varies in an exponential manner with regard to the voltage applied to the gate electrode 106.
FIG. 2 shows a drain current value when a voltage is applied only to the gate electrode 106 of the semiconductor memory device disclosed in Patent Literature 1. As described above, when the voltage applied to the gate electrode 106 is increased linearly, the drain current value varies in an exponential manner. As a result, a channel resistance value varies significantly depending on fluctuation of the voltage applied to the gate electrode 106. Hence, the controllability of the semiconductor memory device disclosed in Patent Literature 1 is poor.